How it's calculated
- One bit is split into time quanta (TQ): 1 sync segment + TSEG1 (propagation + phase segment 1) + TSEG2 (phase segment 2). One TQ = prescaler ÷ CAN clock.
- Sample point = (1 + TSEG1) ÷ total TQ. CiA recommends 87.5% for classic CAN at automotive bit rates; CAN FD usually uses about 80% in the arbitration phase and 70–80% in the data phase.
- SJW (synchronisation jump width) is set to TSEG2, the largest value allowed, which gives the best tolerance to clock differences between nodes.
- CAN FD: the same prescaler in both phases is preferred (CiA 601-3), and a low prescaler (1 or 2) with a 40 or 80 MHz clock gives the finest steps. The transmitter delay compensation offset is set to the data-phase sample point in clock cycles.
Results must be the same sample point on every node in the network. Confirm segment limits in your controller's manual.
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Questions
Why does every node need the same sample point?
Nodes with different sample points sample the same bit at different moments. At high bit rates or on long buses this causes bit errors and error frames that are hard to trace.
Why are some bit rates impossible with my clock?
The clock divided by (prescaler × number of TQ) must equal the bit rate exactly. For example a 10 MHz clock gives 500 kbit/s (20 TQ per bit), but not 800 kbit/s, because 10 MHz ÷ 800 kbit/s = 12.5 clock cycles per bit. A 40 or 80 MHz clock works for all common CAN FD rates.
What is the TDC offset in CAN FD?
At high data rates the transceiver loop delay is longer than a bit. Transmitter delay compensation adds an offset so the sender checks its own bit at the right point. A common starting value is the data-phase sample point measured in CAN clock cycles.
Bringing up a new CAN or CAN FD node?
Dervo engineers configure CAN controllers, validate bit timing across the network and debug error frames on the bench.