CAN and CAN FD bit timing: choosing the prescaler, segments and sample point

Bit timing is one of the first things set when a new ECU joins a CAN network, and one of the hardest problems to find later when it is slightly wrong. Here is how it works and how to choose settings with confidence.

How a CAN bit is built

The CAN controller divides every bit into small steps called time quanta (TQ). One TQ is the prescaler divided by the CAN clock: with a 16 MHz clock and a prescaler of 2, one TQ is 125 ns.

• Sync segment: always 1 TQ, where edges are expected.
• TSEG1: propagation segment plus phase segment 1. It covers the signal delay along the bus and through the transceivers.
• TSEG2: phase segment 2, the time after the sample point.

The bit is sampled at the end of TSEG1, so the sample point = (1 + TSEG1) ÷ total TQ per bit.

A worked example

For 500 kbit/s with a 16 MHz clock: 16 MHz ÷ 500 kbit/s = 32 clock cycles per bit. With a prescaler of 2 that is 16 TQ per bit. Choosing TSEG1 = 13 and TSEG2 = 2 gives (1 + 13) ÷ 16 = 87.5%, a common choice at 500 kbit/s in automotive network specifications. Always use the value your OEM or network specification gives.

Most controllers store each value minus 1, so the registers hold BRP = 1, TSEG1 = 12 and TSEG2 = 1. Always check your controller's manual.

Synchronisation jump width (SJW)

Each node re-synchronises on edges to correct small clock differences. SJW limits how far it may move per edge. Setting SJW as large as TSEG2 allows gives the best tolerance to oscillator differences between nodes.

CAN FD: two bit rates

CAN FD uses a nominal bit rate for arbitration and a faster data bit rate for the payload. Good practice from CiA 601-3:

• Use the same prescaler in both phases, ideally 1 or 2.
• Use a 40 or 80 MHz CAN clock, which divides evenly into all common CAN FD rates.
• Use about 80% sample point in the arbitration phase and 70–80% in the data phase, as your OEM specification defines.
• Set transmitter delay compensation for data rates above about 1 Mbit/s. A common start value for the offset is the data-phase sample point measured in clock cycles.

Example: 80 MHz clock, 500 kbit/s and 2 Mbit/s, prescaler 2. Nominal: 80 TQ with TSEG1 = 63 and TSEG2 = 16 (80%). Data: 20 TQ with TSEG1 = 14 and TSEG2 = 5 (75%).

Common mistakes

• Different sample points on different nodes. Every node on the bus must use the same nominal sample point.
• A clock that cannot reach the bit rate exactly. For example, 10 MHz ÷ 800 kbit/s = 12.5 clock cycles per bit, so 800 kbit/s is impossible with a 10 MHz clock.
• Copying register values from another controller family without checking whether they are stored minus 1.
• Forgetting transmitter delay compensation at 2 Mbit/s and above.

Try it

Our free CAN bit timing calculator lists every valid prescaler and segment setting for your clock, best first, with register values and the CAN FD delay compensation offset.